1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and, more particularly, to a semiconductor memory device is using floating body cells.
2. Description of the Related Art
With the introduction of a large-scale integration semiconductor device manufacturing process, the most difficult technical problem in the manufacture of DRAM, in which a unit memory cell is formed of one transistor and one capacitor, is to maintain a sufficient data retention time while improving a short channel effect and to fabricate a capacitor having a sufficient capacitance while minimizing dielectric leakage in a narrow area. In particular, the manufacture of a capacitor capable of ensuring reliability while satisfying capacitance necessary for the operation of DRAM has reached the limit of its technology. This technology has drawbacks in terms of process. To solve this problem, active research has been conducted into 1T-DRAM with a memory cell formed of one transistor using the floating body effect of a transistor, as disclosed in, for example, U.S. Patent Application Publication No. US 20070058427 A1.
Meanwhile, in the case of the existing 1T-1C DRAM device, charges are stored in the capacitor. In contrast, a Floating Body Cell (FBC) adopted as the memory cell of 1T-DRAM is used as memory using the change in the threshold voltage (VT) occurring when charges are stored in the body of a transistor. For example, when the transistor operates, impact ionization occurs and, at the same time, holes are created in the floating body. The threshold voltage of the transistor changes depending on whether the created holes are stored or not. This effect is referred to as the “floating body effect.” Data “1” or “0” is read based on the change in the is transistor current depending on the change in the threshold voltage. In order to store charges, that is, holes in the floating body, a channel region must be floated. For this purpose, a semiconductor substrate having a Silicon-On Isolator (SOI) structure also known as a “Silicon-On-Insulator” structure, in which an insulating layer is buried is generally used.
FIGS. 1A and 1B are a circuit diagram and a layout diagram of the cell array of a semiconductor memory device using FBCs as memory cells. FIGS. 1A and 1B illustrate that in a memory cell array in which source lines SLl−1 and SLl+1 are used in common and there are separately formed bit lines BL0 and BL1, one dummy line 3 is formed between memory cells. In this case, the cell area is 6F2. In the case where the minimum area 6F2 is used in order to construct the memory cell array, two word lines WLn and WLn+1 are arranged in each active region 1, and respective active regions 1 are spaced apart from each other at a distance D, which is half the pitch of the word lines, in order to avoid data interference between the cells.
In this case, the dummy line 3 is used as a barrier when landing plug contacts are formed after a gate forming process, or is inserted in order to maintain the uniformity of gate patterning. However, in the case where the memory cell array is formed as described above, it is difficult to form the patterns of the active regions because the distance D between the active regions is narrow as shown in FIG. 1B. That is, if the ratio of the long-axis distance L of the active region 1 in a longitudinal direction to the inter-axis distance D is small (typically, L:D=2:1), Depth-of-Focus (DOF) margin in the photolithography process drastically decreases, so that the active regions 1 may not be separated from and may come into contact with is each other. This problem is more pronounced in the case where a process technology, in particular, a 100 nm or less than 100 nm process technology, is used. Although this problem may be solved by using a dual exposure process or a dual patterning process which uses a mask twice, the manufacturing process becomes complicated and the manufacturing cost increases.